Since the invention of the integrated circuit (IC), the semiconductor industry has experienced continued rapid growth due to continuous improvements in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, which allows more components to be integrated into a given area.
The past few decades have also seen many shifts in semiconductor packaging that have impacted the entire semiconductor industry. The introduction of surface-mount technology (SMT) and ball grid array (BGA) packages were generally important steps for high-throughput assembly of a wide variety of IC devices, while at the same time allowing for reduction of the pad pitch on the printed circuit board (PCB). Conventionally packaged ICs have a structure basically interconnected by fine gold wire between metal pads on the die and electrodes spreading out of molded resin packages. On the other hand, some BGA packages rely on bumps of solder to provide an electrical connection between contacts on the die and contacts on a packaging substrate, such as a silicon interposer, an organic substrate, a ceramic substrate, or the like, and rely on balls of solder to make an electrical connection between contacts on the packaging substrate and a PCB. Similarly, some chip size packaging (CSP) packages rely on balls of solder to make an electrical connection directly between contacts on the die and a PCB, another die/wafer, or the like. These techniques may also be used to interconnect multiple dies and/or wafers. The various layers making up these interconnections typically have different coefficients of thermal expansion (CTEs). As a result, a relatively large stress may be exhibited on the joint area, which often causes cracks to form.